Recent Research Projects
Power integrity (PI) has become one of the major concerns in electronic systems, especially for high-speed circuits or mixed-signal systems in recent few years. With the requirements of faster digital speed, higher integration, and higher throughput of data communication for electronic systems, the challenge of Power integrity would be expected to increase. There are several coupled aspects of PI: on the chip, in the chip package, on the circuit board, and in the system. The Center for Electromagnetic Compatibility has been working in this area for many years.
Chip-level Power Distribution Network (PDN) Modeling
Accurate impedance estimation of the power distribution network (PDN) in a system is an efficient criterion to evaluate the system performance in high-speed and high-performance semiconductor system design. Full-wave simulation methods could take a significant amount of time and resources for computation of chip level PDN impedance because the geometry of the chip level PDN is quite complex. To accurately and quickly estimate the on-chip PDN impedance, we are developing an equivalent circuit model for chip level PDN based on partial element equivalent circuit (PEEC) method and Layered Green's Function.
Power Integrity of 2.5D and 3D IC Systems
In 2.5D and 3D IC systems, the power distribution network normally consists of many layers of power/ground (P/G) grids and P/G TSVs as interconnection between the P/G layers. The impedance of the on-die PDN depends on the P/G grid, P/G TSVs and P/G grid in the silicon interposer. As there will be hundreds or thousands of P/G TSVs embedded in the 2.5D/3D IC, the equivalent capacitances from the TSVs will play an important role on the total impedance. The goal of the power integrity analysis of this research is to model the PDN impedance in the system with 2.5D/3D IC from on-die P/G grid and TSVs to the P/G plane on PCB. The influence of bias-dependency and temperature-dependency of the TSVs on the impedance of the system PDN will be investigated to illustrate that variations on the bias voltage and temperature could not be neglected to cause power integrity issues in the 2.5D/3D IC systems. Design guidelines on the on-die PDN to reduce the risk of such issues will be continuously under investigation by Missouri S&T EMC Laboratory.
Voltage and temperature dependency of the TSV capacitance
A pre-layout tool based on cavity model and PPP is built in the multi-layered PCB PDN area. In the algorithm, the whole geometry could be divided into four pieces and different methods are used to calculate different parts. With limited input geometry details, the tool could automatically decide where to put the decoupling capacitors, which decoupling capacitors should be added and how to complete a PCB PDN perfectly. Then the pre-layout tool will provide geometry details, the calculation results of PDN impedance of the design and a feedback for the users. The process is quite time-saving and convenient.
PCB Decap Placement Optimization
With increasing board densities and rising digital speeds, the parasitics associated with PCB power distribution networks (PDN) make ensuring adequate power delivery to board ICs a more and more difficult task. Decoupling capacitors (decaps) are commonly used to reduce the impedance seen from the IC by creating a low impedance current return path. Realistic designs however, may have hundreds of decap placement locations and a proportionally exponential number of decap placement patterns. This makes finding the placement pattern that can both meet the designer’s voltage ripple limits and with the most minimal cost, very difficult. Research in the lab is ongoing to develop optimization methods like genetic algorithms and machine learning models to automate and quickly find the most cost-effective decap placement pattern.