Recent Research Projects
Signal Integrity
Signal Integrity (SI) issues are those that affect signal fidelity when a signal is transmitted from a driver to a receiver. Sufficient signal fidelity is needed in order to effectively pass information with a low error rate. The Center for Electromagnetic Compatibility has been working in this area to improve the signal integrity for high-speed systems.
⦁ Comparison of SPDR method and stripline based metho
Normally, the material properties of PCB are measured by split post dielectric resonator (SPDR) method from the vendor. But the extracted Dk/Df of material by SPDR method are quite different from the Dk/Df extracted by the strip line based method for inhomogeneous material. One potential reason for this discrepancy is from the mode difference of these two methods. The SPDR method works in TE10 mode while the stripline based method works in TEM mode.
PCB Material Characterization
Accurate PCB material characterization is essential for high-speed digital design since wrong input material properties would lead to wrong design decisions. The Center for Electromagnetic Compatibility has been studying this problem for several years. Work in this area falls primarily into the following categories:
⦁ Accurate Extraction for Dielectric constant (Dk), Loss Tangent (Df) and Copper Surface Roughness
The goal in this direction is to develop a methodology feasible for the extraction of PCB material properties for high-speed PCBs. Several different algorithms have been proposed in this work and validated through measurement-based analysis. In addition, the associated tools with user-friendly UI were generated for engineering applications. This work is continuing with the concentration on more accurate separation between dielectric and conductor loss for the ultra-low loss materials using the edge-cutting technologies.
⦁ Extraction of Dk Values for Core and Prepreg in a PCB Stripline
The far-end crosstalk (FEXT) is attributed to the material inhomogeneity and signal conductor proximity effect in which inhomogeneous dielectric is the dominant factor. This necessitates the characterization of Dkcore and Dkprepreg. Two different algorithms have been proposed in this work and associated tools have been developed. Furthermore, novel design guidelines for FEXT mitigation are generated based on this study.
⦁ Characterization of the Stripline with Inhomogeneous Dielectric Layers (IDL)
In the fabrication procedure of the multilayer PCBs, the dielectric layers are laminated with epoxy resin and glass bundles. Normally, the stripline is considered as a 2-layer model with core and prepreg layers. The resin pocket plays an important role in the stripline modeling. The 3-layer model can provide a better description of the actual performance of the stripline. With the analysis of the per-unit-length capacitance, the material of the stripline can be extracted
Side view of SPDR in HFSS
Electric field distribution in the sample
⦁ Comparison of SPDR method and stripline based metho
Normally, the material properties of PCB are measured by split post dielectric resonator (SPDR) method from the vendor. But the extracted Dk/Df of material by SPDR method are quite different from the Dk/Df extracted by the strip line based method for inhomogeneous material. One potential reason for this discrepancy is from the mode difference of these two methods. The SPDR method works in TE10 mode while the stripline based method works in TEM mode.
Power Supply Induced Jitter (PSIJ)
With the increase of I/O interface speeds to multi-gigabit or even higher data rates, the timing jitter problem becomes one of the most crucial challenges associated with the shrinking timing budget. Power supply induced jitter (PSIJ) is introduced into the system as the voltage ripple can cause significant delay change in the transmitters and receivers and is an essential part of the timing jitter. The Center for Electromagnetic Compatibility has been studying this problem for several years. Work in this area now falls primarily into improving IBIS model simulation accuracy by considering the effect of voltage supply noise.
Current IBIS model cannot reflect the effect of power rail voltage noise on switching edge timing change. Even the power-aware IBIS model which considers the gate modulation effect only accounts for the effect of pull-up/pull-down voltage.
The basic idea is to modify the driver switching coefficients Ku/Kd as a function of time averaged power rail voltage Vcc(t) and introduce correction coefficients as a function of time. By considering different cases, the modification algorithm can have a good generalization.